High speed, low power all CMOS thermometer-to-binary demultiplexer

ABSTRACT

High speed, low power all CMOS thermometer-to-binary demultiplexer. A received signal undergoes digital sampling (e.g., as within an ADC) to generate a signal that subsequently undergoes encoding (e.g., transformation from thermometer encoded data to binary encoded data) and de-multiplexing. Two separate de-multiplexing stages are employed when performing combined encoding and de-multiplexing. In addition, the individual DEMUXs of the two stages are clocked using a distributed clock generation architecture, such that, reset and time-interleaving is controlled on the ADC clock generator. The thermometer-to-binary encoders are placed very close to the input stage which facilitates very fast data rates while consuming relatively lower power.

BACKGROUND OF THE INVENTION

1. Technical Field of the Invention

The invention relates generally to communication systems; and, moreparticularly, it relates to demultiplexing of signals within suchcommunication systems.

2. Description of Related Art

Data communication systems have been under continual development formany years. Within certain communication systems, different types ofcoded signals are employed, and it is oftentimes desirable to transforma signal from a first coded signal type to a second coded signal type.One example of this transformation from a first coded signal type to asecond coded signal type involves transforming a thermometer encodedsignal to a binary coded signal.

The prior art means for performing this thermometer to binarytransformation have a number of deficiencies including occupying asignificant amount of real estate and also consuming a significantamount of power.

FIG. 6A and FIG. 6B illustrate prior art and ideal, non-realizableembodiments of combined demultiplexing and thermometer encoding.

Referring to the prior art embodiment 601 of FIG. 6A, this traditionalarchitecture of a thermometer-to-binary DEMUX encoder (which can bereferred to as a DEMUX encoder) de-multiplexes the thermometer encodeddata firstly using a 1 to 4 DEMUX and then performs thethermometer-to-binary encoding thereon using an encoder.

One embodiment of such a prior art architecture uses a 1 to 4 DEMUXwhich contains 5 latches operating at frequency F, and 10 latchesoperating at F/2 with the number of bits being 63 through the entireDEMUX. The estimated power consumption, P, is calculated as follows:P=(N _(bits))×(# of latches)×(frequency).P=63×5×F+63×10×(F/2)=630F.

Referring to the ideal, yet non-realizable embodiment 602 of FIG. 6B, abest approach would be to place the encoder prior to the input of theDEMUX for a potential power savings as calculated as follows:P=(N _(bits))×(# of latches)×(frequency).P=6×5×F+6×10×(F/2)=60F.

This is a power savings of 90%, but this embodiment 602 is simply notalways possible or realizable, especially for high speed applications.

There exists a need in the art for less power consumptive, yetrealizable architectures for performing combined de-multiplexing andencoding while supporting increased/higher operational rates and dataspeeds.

BRIEF SUMMARY OF THE INVENTION

The present invention is directed to apparatus and methods of operationthat are further described in the following Brief Description of theSeveral Views of the Drawings, the Detailed Description of theInvention, and the claims. Other features and advantages of the presentinvention will become apparent from the following detailed descriptionof the invention made with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 illustrates an embodiment of a communication system.

FIG. 2 illustrates an embodiment of a demultiplexer (DEMUX).

FIG. 3 illustrates an embodiment of a DEMUX and a multiplexer (MUX)implemented to support parallel processing of an input signal.

FIG. 4 illustrates an embodiment of thermometer encoding.

FIG. 5A, FIG. 5B, FIG. 5C, and FIG. 5D illustrate various embodimentsrelating decimal information to thermometer encoded information tobinary encoded information.

FIG. 6A and FIG. 6B illustrate prior art and ideal, non-realizableembodiments of combined demultiplexing and thermometer encoding.

FIG. 7 illustrates an embodiment of a multi-stage demultiplexing andencoding.

FIG. 8 illustrates an alternative embodiment of a multi-stagedemultiplexing and encoding.

FIG. 9 illustrates an embodiment of a multi-stage demultiplexing andthermometer encoding.

FIG. 10 illustrates an embodiment of a timing diagram of signals withinFIG. 9.

FIG. 11 illustrates an embodiment of time-interleaved clock path andreset within an apparatus employing a single divider with verticaltiming.

FIG. 12 illustrates an embodiment of time-interleaved clock path andreset within an apparatus employing multiple, distributed dividershaving coordinated startup.

FIG. 13 illustrates an embodiment of a method for demultiplexing andthermometer encoding.

DETAILED DESCRIPTION OF THE INVENTION

A novel architecture and approach to performing combined de-multiplexingand encoding is presented herein.

One application context that can employ such architecture may employhigh speed time-interleaved flash analog to digital converters (ADCs).In such devices, the act of de-multiplexing the flash comparator outputsand converting the bits from thermometer encoded data to binary encodeddata (e.g., from thermometer to binary encoding) can consume asignificant portion of the overall ADC power.

The novel architecture and approach presented herein places thethermometer-to-binary encoder as close to the input stage as possiblewhile pushing the functionality after the data has been converted (to abinary format) to a lower number of bits and data rate. This reduces thearea, and power consumption of the overall circuit. In addition, thenovel architecture removes the timing dependence between each individualDEMUX encoder by placing distributed, local dividers throughout thecircuitry for each DEMUX to remove potential race conditions that canarise during reset.

This architecture and approach presented herein can be employed within awide variety of communication systems, some types of which are describedbelow.

The goal of digital communications systems is to transmit digital datafrom one location, or subsystem, to another either error free or with anacceptably low error rate. As shown in FIG. 1, data may be transmittedover a variety of communications channels in a wide variety ofcommunication systems: magnetic media, wired, wireless, fiber (e.g.,optical fiber), copper, and/or other types of media as well.

FIG. 1 is a diagram illustrating an embodiment of a communication system100.

Referring to FIG. 1, this embodiment of a communication system 100 is acommunication channel 199 that communicatively couples a communicationdevice 110 (including a transmitter 112 having an encoder 114 andincluding a receiver 116 having a decoder 118) situated at one end ofthe communication channel 199 to another communication device 120(including a transmitter 126 having an encoder 128 and including areceiver 122 having a decoder 124) at the other end of the communicationchannel 199. In some embodiments, either of the communication devices110 and 120 may only include a transmitter or a receiver. There areseveral different types of media by which the communication channel 199may be implemented (e.g., a satellite communication channel 130 usingsatellite dishes 132 and 134, a wireless communication channel 140 usingtowers 142 and 144 and/or local antennae 152 and 154, a wiredcommunication channel 150, and/or a fiber-optic communication channel160 using electrical to optical (E/O) interface 162 and optical toelectrical (O/E) interface 164)). In addition, more than one type ofmedia may be implemented and interfaced together thereby forming thecommunication channel 199.

In addition, more than one type of media may be implemented andinterfaced together thereby forming the communication channel 199. It isnoted also that either one of both of the communication device 110 andthe communication device 120 can include a hard disk drive (HDD) (or becoupled to a HDD).

It is also noted that either one of both of the communication device 110and the communication device 120 can include a demultiplexer (DEMUX) inaccordance with any of the embodiments and/or aspects presented herein.For example, the communication device 110 can include a DEMUX 110 a, andthe communication device 120 can include a DEMUX 120 a.

The signals employed within this embodiment of a communication system100 can be of any variety of types of signals, including uncodedsignals, signals employing uncoded modulation, Reed-Solomon (RS) codedsignals, LDPC (Low Density Parity Check) coded signal, turbo codedsignals, turbo trellis coded modulation (TTCM), and/or coded signalsgenerated using some other error correction coding (ECC).

Also, any of a very wide variety of applications that performtransferring of signals from one location to another (e.g., includingfrom a first location to a HDD, or from the HDD to another location) canbenefit from various aspects of the invention, including any of thosetypes of communication devices and/or communication systems depicted inFIG. 1. Moreover, any other types of devices, methods, and applicationsthat employ a DEMUX, or employ a DEMUX and perform encoding (e.g.,including thermometer encoding) of a signal in accordance with anyembodiment and/or aspect presented herein can also benefit from variousaspects of the invention.

Such a DEMUX 110 a or DEMUX 120 a, or any embodiment of a DEMUX inaccordance with any embodiment and/or aspects described herein, can beimplemented anywhere within a device where a signal is being processed.For example, in some applications, it is desirable to performdemultiplexing of a signal to effectuate parallel processing of theindividual components of that signal. An incoming signal can betransformed (e.g., de-serialized) into multiple signals such that eachof the multiple signals corporately include all information of theincoming signal. In this way, a number of parallel-implementedprocessors and/or modules can each operate on one of the multiplesignals.

Another application may include a device that performs serializationand/or de-serialization (e.g., a SERDES performs both serialization andde-serialization), multiplexing and/or de-multiplexing in which multiplesignals need to be processed together. Again, a number ofparallel-implemented processors and/or modules could process thosesignals (e.g., undergoing serialization and/or de-serialization,multiplexing and/or de-multiplexing) during a same time period.

Generally speaking, such a DEMUX can be employed within any device inwhich a signal is desired to undergo de-multiplexing. Moreover, such aDEMUX can be implemented in cooperation with other processors and/ormodules, including encoders (e.g., which could be thermometer encodersimplemented to perform thermometer to binary transformations, or viceversa) as well without departing from the scope and spirit of theinvention.

FIG. 2 illustrates an embodiment of a demultiplexer (DEMUX) 200. TheDEMUX 200 receives an input signal, and generates a number of outputsignals (depicted as 1, 2, . . . , up to m, where m is an integer).Also, a select signal can be employed to select one of the outputsignals at a particular time. In some embodiments, different of outputsignals are selected at different times (e.g., output signal 1 at time1, output signal 2 at time 2, and so on) as directed by the selectsignal that may itself be changing as a function of time.

Such a DEMUX 200 may be implemented within any of a wide variety ofapplications including a de-serializer that receives a serial signal andgenerates a parallel signal (e.g., the output signal 1-m) that includesall of the information within the serial signal. This may be viewed asbeing a serial to parallel conversion.

Another application in which the DEMUX 200 may be implemented is anapparatus that performs thermometer to binary encoding in which athermometer encoded signal undergoes transformation to generate a binaryencoded signal. Various embodiments depicting this form of processingare described herein.

FIG. 3 illustrates an embodiment of a DEMUX and a multiplexer (MUX)implemented to support parallel processing 300 of an input signal. Thisis yet another application in which a DEMUX (shown as being a 1 to nDEMUX) may be implemented. A DEMUX receives an input signal, andgenerates a number of output signals (depicted as 1, 2, up to n, where nis an integer). Also, a select signal can be employed to select one ofthe output signals at a particular time. In some embodiments, differentof output signals are selected at different times (e.g., output signal 1at time 1, output signal 2 at time 2, and so on) as directed by theselect signal that may itself be changing as a function of time.

A parallel processing module 320, that includes a number of processors(e.g., as shown by processor 321, processor 322, and up to processor323, that considered together may be more than 3 processors), operateson each of the signals output from the DEMUX. This parallel operation oneach of the signals output from the DEMUX allows the ability to processeach of these individual signals at a slower rate (e.g., using a lowerfrequency and/or clock) that the rate at which the input signal isreceived while still maintaining a common, steady state flow ofinformation through the system. For example, the frequency at which theparallel processing module 320 operates may be a frequency f2, that isdifferent from a frequency f1 at which the input signal is received orprocessed, and the frequency f2 may be less than the frequency f1.

After being processing within the parallel processing module 320, thesignals output there from can be provided to a MUX that (shown as beingan n to 1 MUX) combines the signals received by the MUX it and/orselects one of the signals received by the MUX. The output signal maythen be processed within a domain having the frequency f1 or a frequencyf3 that is different from the frequency f2 and the frequency f1. Thefrequency f3 may be greater than the frequency f2.

This diagram shows yet another embodiment in which a DEMUX (and/or aMUX) may be employed. Generally speaking, the various embodiments of aDEMUX as described herein can be employed within any desired devicevarious types of communication devices where the generation of multipleoutput signals from one or more input signals is being performed. Forexample, while many of the embodiments depicted herein show a DEMUX thatreceived only 1 input signals, it is noted that the principles andaspects presented herein may also be applied to a DEMUX that receivesmore than one input signal (e.g., 2 or more input signals).

It is also noted that, in an alternative embodiment, the MUX need not beimplemented. For example, an input signal can be processed to generatethe output signals (depicted as 1, 2, up to n, where n is an integer)for subsequent parallel processing within the parallel processing module320. This alternative embodiment could be similar to what is depicted inthe diagram with at least one difference being that these parallelsignals processed by the parallel processing module 320 are not providedto the MUX.

FIG. 4 illustrates an embodiment of thermometer encoding 400. Generallyspeaking, a thermometer encoded signal has analogous properties of athermometer employed for measuring temperature as is generally known.For example, considering the table at the top of the diagram, anembodiment including 8 distinct values are shown with reference to theirdecimal counterparts (e.g., 0, 1, 2, and so on to 7).

Since this embodiment includes 8 distinct values, then 7 distinct bitsare employed in the thermometer encoded signal to represent all of these8 distinct values decimal counterparts. Each individual bit of thecorresponding thermometer encoded signal values are employed torepresent its decimal counterpart as follows:

0 in decimal is represented in thermometer encoding as 7 successive 0s.

1 in decimal is represented in thermometer encoding as a 1 located inthe least significant bit (LSB) location preceded by all 0s in the 6other bit positions.

2 in decimal is represented in thermometer encoding as a 1 located inthe two LSB locations preceded by all 0s in the 5 other bit positions.

3 in decimal is represented in thermometer encoding as a 1 located inthe three LSB locations preceded by all 0s in the 4 other bit positions.

The remainder of the correspondence can be seen in the diagram.

As can be seen, 1 bit position is made to be a value of 1 in athermometer encoded signal to generate a corresponding 1 (decimal)valued signal.

As can be seen, 2 bit positions are made to be a value of 1 in athermometer encoded signal to generate a corresponding 2 (decimal)valued signal.

As can be seen, 3 bit positions are made to be a value of 1 in athermometer encoded signal to generate a corresponding 3 (decimal)valued signal.

The thermometer encoded signal output may be viewed as being acorresponding cumulative signal, in that, each successively largernumber includes all 1 valued bits in the lower significant bit locationsas each smaller number than it. For example, 1 (decimal), whenrepresented in a thermometer encoded signal, includes a 1 valued bit inthe least significant bit location. 2 (decimal), when represented in athermometer encoded signal, includes 1 valued bits in the leastsignificant bit location and the next more significant bit location, and2 (decimal), when represented in a thermometer encoded signal, includes1 valued bits in the least significant bit location and in the next 2more significant bit location.

FIG. 5A, FIG. 5B, FIG. 5C, and FIG. 5D illustrate various embodimentsrelating decimal information to thermometer encoded information tobinary encoded information.

Referring to FIG. 5A, an embodiment of a thermometer code that includes7 distinct digits (8 distinct values, in that, all bits being 0 isactually 0) is shown.

Referring to FIG. 5B, an embodiment of a thermometer code that includes10 distinct digits (11 distinct values, in that, all bits being 0 isactually 0) is shown.

Referring to FIG. 5C, an embodiment of a thermometer code that includes15 distinct digits (16 distinct values, in that, all bits being 0 isactually 0) is shown.

Referring to FIG. 5D, an embodiment of a thermometer code that includes19 distinct digits (20 distinct values, in that, all bits being 0 isactually 0) is shown.

As can be seen, transforming thermometer encoded information to binaryencoded information need not only include a total number of distinctvalues such that the largest valued binary need not be composed of all1s.

For more detailed description of the prior art embodiments of FIG. 6Aand FIG. 6B, the reader is directed to the “DESCRIPTION OF RELATED ART”section herein.

FIG. 6A and FIG. 6B illustrate prior art and ideal, non-realizableembodiments of combined demultiplexing and thermometer encoding.

FIG. 7 illustrates an embodiment of a multi-stage demultiplexing andencoding 700. This embodiment includes an analog to digital converter(ADC) samples an incoming analog signal at some sampling rate togenerate a digital signal. The digital signal is then provided to aDEMUX (shown as performing a ‘1 to a’ transformation, in which a is aninteger). Each of the signals output from the DEMUX is provided to acorresponding encoder (e.g., shown as encoder 1, encoder 2, and up toencoder a). A stage 1 includes the first DEMUX (1 to a) and each of theencoders 1-a. A stage 2 includes a number of DEMUXs (each shown asperforming a ‘1 to b’ transformation, in which b is an integer). It isnoted that alternative embodiments could include a number of DEMUXs suchthat each DEMUX could perform a different transformation, e.g., a ‘1 tob’ transformation, a ‘1 to c’ transformation, a ‘1 to d’ transformation,etc., in which b, c, d, etc. are integers).

The stage 2 of this embodiment includes the DEMUXs (that each performthe 1 to b transformation) to generate a number of output signals.

If desired in some embodiments, the ADC can sample its incoming signalat a first clock, and the elements within stage 1 can operate at asecond clock. The elements in the stage 2 can also operate at a thirdclock as well without departing from the scope and spirit of theinvention.

In even certain embodiments, the encoders 1-a may be thermometerencoders that process thermometer coded data thereby generating binarycoded data.

FIG. 8 illustrates an alternative embodiment of a multi-stagedemultiplexing and encoding 800. Comparing this embodiment to the priorart embodiment of FIG. 6A that employs 5 latches and outputs the data ona common clock edge, this alternate architecture is to push the encoderinto the DEMUX path to reduce the number of latches needed for the lowerDEMUX stages.

Performing analogous power calculations as shown above, the estimatedpower for this embodiment is as follows:P=(N _(bits))×(# of latches)×(frequency).P=63×5×F+6×10×(F/2)=375F.

This is a power savings of 45% compared to the prior art embodiment 601of FIG. 6A.

FIG. 9 illustrates an embodiment of a multi-stage demultiplexing andthermometer encoding 800. This embodiment includes an ADC that digitallysamples a signal at a first clock (e.g., shown as clk=2F). A firstde-multiplexing stage includes a number of flip-flops (FFs) and a numberof thermometer encoders. This embodiment shows the first de-multiplexingstage having 2 FFs and 2 thermometer encoders, though more FFs and/orthermometer encoders could also be employed in other embodiments.

Within the first de-multiplexing stage, a first FF, that is clocked at asecond clock, receives the digitally sampled signal from the ADC. Also,a second FF, that is clocked at an inverted version of the second clock,receives the digitally sampled signal from the ADC. A first thermometerencoder transforms thermometer coded data output from the first FF tobinary data, and a second thermometer encoder transforms thermometercoded data output from the second FF of the first plurality of FFs tobinary data.

The first de-multiplexing stage is coupled to a second de-multiplexingstage, and the second de-multiplexing stage also includes a number ofFFs. Within the second de-multiplexing stage, a first FF, that isclocked at a third clock that is generated using the first clock,receives the binary data output from the first thermometer encoder. Alsowithin the second de-multiplexing stage, a second FF, that is clocked atan inverted version of the third clock, receives the binary data outputfrom the first thermometer encoder. A third FF (in the secondde-multiplexing stage), that is clocked at a fourth clock that isgenerated using the second clock, receives the binary data output fromthe second thermometer encoder, and a fourth FF (in the secondde-multiplexing stage), that is clocked at an inverted version of thefourth clock, receives the binary data output from the secondthermometer encoder. Then, de-multiplexed binary data (shown as A, B, C,and D) are output from the FFs within the second de-multiplexing stage.

The apparatus of this diagram is implemented to perform combinedthermometer-to-binary demultiplexing and encoding. The signal receivedby the ADC may be viewed as being thermometer coded data, and thisthermometer coded data is output from the ADC to each of the first FFand the second FF of the first de-multiplexing stage. This inputthermometer coded data is de-multiplexed using the rising and fallingedge of a divide by 2 clock (e.g., a second clock signal, that is shownas clk2, which has a frequency F that is one half of the first clocksignal at which the ADC is clocked).

Other implemented FFs operate to generate a third clock signal and afourth clock signal based on the second clock signal that are used toclock the FFs of the second de-multiplexing stage. Each of the thirdclock signal and the fourth clock signal have a frequency of F/2, whichis one-fourth of the first clock signal and one-half of the second clocksignal.

The outputs to the second de-multiplexing stage, shown at path 1 andpath 2 in the diagram, are not aligned to one clock domain and areoutput relative to the respective rising or falling clock edges as shownin the timing diagram of FIG. 10.

FIG. 10 illustrates an embodiment of a timing diagram 1000 of signalswithin FIG. 9.

Considering FIG. 9 and FIG. 10 in conjunction with one another andconsidering an embodiment of the first de-multiplexing stage thatoperates on 63-bit thermometer coded data, the 63-bit thermometer codeddata is passed through a combinational logic bubble detector and encoderthat converts the 63-bit thermometer coded data to a binary signal,which may be 6-bits in one embodiment. Such an embodiment of a secondde-multiplexing stage then de-multiplexes the output using a divideddown clock (e.g., shown as clk3 and clk4) relative to the edge the datawas output from the first de-multiplexing stage.

For example, path 1 would use the divided down clock relative to thefalling edge and path 2 would use the divided down clock relative to therising edge. This increases the timing margin to the secondde-multiplexing stage by ½F (or F/2) where F is the input clockfrequency. This additional clock domain (or second clock domain) allowsthe thermometer to binary encoder to be placed as close to the input aspossible reducing the overall number of components, area and whileproviding for reduced power consumption. The final de-multiplexed outputis retimed to one final clock domain before being transmitted out as canbe seen in the timing diagram 1000 of FIG. 10.

The embodiment of FIG. 9 (whose timing diagram 1000 is shown in FIG. 10)modifies the architecture depicted in FIG. 8 by replacing the inputDEMUX stage from 5 latches with a DEMUX of 4 latches and having the lastDEMUX stage consist of 8 latches compared to 5.

Performing analogous power calculations as shown above, the estimatedpower for this embodiment is as follows:P=(N _(bits))×(# of latches)×(frequency).P=63×4×F+6×16×(F/2)=300F.

This is a power savings of 52% compared to the prior art embodiment 601of FIG. 6A, and a power savings of 20% compared to the embodiment 800 ofFIG. 8.

Comparing this embodiment of FIG. 9 (whose timing diagram 1000 is shownin FIG. 10) to the prior art embodiment of FIG. 6A that employs 5latches and outputs the data on a common clock edge, the embodiment ofFIG. 9 removes one of the latches and allows the data to be output onboth rising and falling clock edges. The removal of the extra high speedlatch at the input stage reduces the power and area significantly.

In this embodiment of FIG. 9, the use of two different clock domains forthe second DEMUX stage increases the timing margin between the firstDEMUX through the thermometer-to-binary encoder into the second DEMUX.The increase in timing margin is T, where T is the period of the inputdata/clock.

The thermometer-to-binary coders are placed very close to the inputstage to convert the 63-bit lines to 6-bits as to reduce the number ofprocessing components (area) and power.

Also, each DEMUX encoder contains its own, independent clock generatorto remove the timing requirements between each ADC channel and thepotential of race conditions along the various paths. Further details ofthis distributed clock generation architecture are also described withreference to FIG. 12. Such a reset and time-interleaving is controlledon the ADC clock generator where it is local and well controlled.

FIG. 11 illustrates an embodiment of time-interleaved clock path andreset within an apparatus 1100 employing a single divider with verticaltiming. Within a multi-channel architecture that employs a number ofDEMUXs, the time-interleaved nature of the ADC requires each of theDEMUX encoder clock domains to be well defined and maintained.

The apparatus 1100 employs one re-settable clock divider (e.g., shown asdiv2) to generate all the frequency clock domains. The apparatus thenretimes them using a number of D-flip-flops (DFFs) for eachtime-interleaved ADC and DEMUX encoder (FIG. 4 a). This inherentlycreates dependency between each DEMUX encoder and requires that theentire clock chain to be operational at all times, regardless of thecurrent operating mode. In addition, this raises the potential for raceconditions due to the various clock paths and process variations acrossthe clock network.

FIG. 12 illustrates an embodiment of time-interleaved clock path andreset within an apparatus 1200 employing multiple, distributed dividershaving coordinated startup. Again, within a multi-channel architecturethat employs a number of DEMUXs, the time-interleaved nature of the ADCrequires each of the DEMUX/encoder clock domains to be well defined andmaintained.

In contrast to the embodiment employed in the previous embodiment, theapparatus 1200 employs a different reset and clock path in which eachDEMUX encoder has an independent divider to locally generate therequired clocks (e.g., shown as the distributed div2 modules). The startup condition for the DEMUX clock generator, however, has to becoordinated by the time-interleaved clock generator in order to maintaina known timing relationship between the various ADC channels.

With respect to the novel architecture and approaches presented herein,it is noted that this architecture can be used for any ADC bus size forthe thermometer or binary code. The larger the thermometer code, themore significant the power and space savings provided using the novelarchitecture and approaches presented herein. Furthermore, novelarchitecture and approaches presented herein can operate at any datarate. Consequently, the faster the data rate employed within the firststage, the larger the power savings. While many of the illustrativeembodiments also depict a DEMUX level of 1 to 4, it is clearly notedthat any desired DEMUX level can be employed (e.g., greater than 1 to 4,including a DEMUX level of 1 to 16 or a DEMUX level of 1 to 32 couldalso work).

FIG. 13 illustrates an embodiment of a method 1300 for demultiplexingand thermometer encoding. The method 1300 begins by digitally sampling asignal at a first clock rate, as shown in a block 1310.

The method 1300 continues by demultiplexing the digitally sampled signalthereby generating a first plurality of DEMUX signals, as shown in ablock 1320.

The method 1300 continues by performing thermometer encoding of eachDEMUX signal of the first plurality of DEMUX signals thereby generatinga first plurality of binary signals, as shown in a block 1330. Ifdesired, as shown by block 1332, the method 1300 can operate byemploying at least two thermometer encoders (e.g., first thermometerencoder encodes first DEMUX signal and second thermometer encoderencodes second DEMUX signal).

The method 1300 continues by demultiplexing each binary signal of thefirst plurality of binary signals thereby generating a second pluralityof binary signals, as shown in a block 1340. The method 1300 continuesby outputting the second plurality of binary signals, as shown in ablock 1350.

It is noted that the various modules (e.g., encoding modules, decodingmodules, thermometer encoding modules, etc.) described herein may be asingle processing device or a plurality of processing devices. Such aprocessing device may be a microprocessor, micro-controller, digitalsignal processor, microcomputer, central processing unit, fieldprogrammable gate array, programmable logic device, state machine, logiccircuitry, analog circuitry, digital circuitry, and/or any device thatmanipulates signals (analog and/or digital) based on operationalinstructions. The operational instructions may be stored in a memory.The memory may be a single memory device or a plurality of memorydevices. Such a memory device may be a read-only memory, random accessmemory, volatile memory, non-volatile memory, static memory, dynamicmemory, flash memory, and/or any device that stores digital information.It is also noted that when the processing module implements one or moreof its functions via a state machine, analog circuitry, digitalcircuitry, and/or logic circuitry, the memory storing the correspondingoperational instructions is embedded with the circuitry comprising thestate machine, analog circuitry, digital circuitry, and/or logiccircuitry. In such an embodiment, a memory stores, and a processingmodule coupled thereto executes, operational instructions correspondingto at least some of the steps and/or functions illustrated and/ordescribed herein.

The present invention has also been described above with the aid ofmethod steps illustrating the performance of specified functions andrelationships thereof. The boundaries and sequence of these functionalbuilding blocks and method steps have been arbitrarily defined hereinfor convenience of description. Alternate boundaries and sequences canbe defined so long as the specified functions and relationships areappropriately performed. Any such alternate boundaries or sequences arethus within the scope and spirit of the claimed invention.

The present invention has been described above with the aid offunctional building blocks illustrating the performance of certainsignificant functions. The boundaries of these functional buildingblocks have been arbitrarily defined for convenience of description.Alternate boundaries could be defined as long as the certain significantfunctions are appropriately performed. Similarly, flow diagram blocksmay also have been arbitrarily defined herein to illustrate certainsignificant functionality. To the extent used, the flow diagram blockboundaries and sequence could have been defined otherwise and stillperform the certain significant functionality. Such alternatedefinitions of both functional building blocks and flow diagram blocksand sequences are thus within the scope and spirit of the claimedinvention.

One of average skill in the art will also recognize that the functionalbuilding blocks, and other illustrative blocks, modules and componentsherein, can be implemented as illustrated or by discrete components,application specific integrated circuits, processors executingappropriate software and the like or any combination thereof.

Moreover, although described in detail for purposes of clarity andunderstanding by way of the aforementioned embodiments, the presentinvention is not limited to such embodiments. It will be obvious to oneof average skill in the art that various changes and modifications maybe practiced within the spirit and scope of the invention, as limitedonly by the scope of the appended claims.

1. An apparatus, comprising: an analog to digital converter (ADC) thatdigitally samples a signal at a first clock; a first de-multiplexingstage that includes a first plurality of flip-flops (FFs) and aplurality of thermometer encoders, wherein: a first FF of the firstplurality of FFs, that is clocked at a second clock, receives thedigitally sampled signal from the ADC; a second FF of the firstplurality of FFs, that is clocked at an inverted version of the secondclock, receives the digitally sampled signal from the ADC; a firstthermometer encoder of the plurality of thermometer encoders transformsthermometer coded data output from the first FF of the first pluralityof FFs to binary data; and a second thermometer encoder of the pluralityof thermometer encoders transforms thermometer coded data output fromthe second FF of the first plurality of FFs to binary data; and a secondde-multiplexing stage that includes a second plurality of FFs, wherein:a first FF of the second plurality of FFs, that is clocked at a thirdclock that is generated using the second clock, receives the binary dataoutput from the first thermometer encoder; a second FF of the secondplurality of FFs, that is clocked at an inverted version of the thirdclock, receives the binary data output from the first thermometerencoder; a third FF of the second plurality of FFs, that is clocked at afourth clock that is generated using the second clock, receives thebinary data output from the second thermometer encoder; and a fourth FFof the second plurality of FFs, that is clocked at an inverted versionof the fourth clock, receives the binary data output from the secondthermometer encoder; and wherein: de-multiplexed binary data are outputfrom the second plurality of FFs.
 2. The apparatus of claim 1, wherein:a rate of the second clock is one-half of a rate of the first clock; anda rate of the third clock is one-half of a rate of the second clock. 3.The apparatus of claim 1, wherein: the second plurality of FFs includes:a fifth FF, coupled to the first FF of the second plurality of FFs, thatoutputs binary data there from on a falling edge or rising edge of thethird clock; and a sixth FF, coupled to the second FF of the secondplurality of FFs, that outputs binary data there from on a falling edgeor rising edge of the third clock.
 4. The apparatus of claim 1, wherein:the second plurality of FFs includes: a fifth FF, coupled to the thirdFF of the second plurality of FFs, that outputs binary data there fromon a falling edge or rising edge of the fourth clock; and a sixth FF,coupled to the fourth FF of the second plurality of FFs, that outputsbinary data there from on a falling edge or rising edge of the fourthclock.
 5. The apparatus of claim 1, wherein: the second plurality of FFsincludes: a fifth FF, coupled to the first FF of the second plurality ofFFs, that outputs binary data there from on a falling edge or risingedge of the third clock; a sixth FF, coupled to the second FF of thesecond plurality of FFs, that outputs binary data there from on afalling edge or rising edge of the third clock; a seventh FF, coupled tothe third FF of the second plurality of FFs, that outputs binary datathere from on a falling edge or rising edge of the fourth clock; aeighth FF, coupled to the fourth FF of the second plurality of FFs, thatoutputs binary data there from on a falling edge or rising edge of thefourth clock; and the fifth FF, the sixth FF, the seventh FF, and theeighth FF output their corresponding binary data simultaneously with oneanother.
 6. The apparatus of claim 1, wherein: the first FF of thesecond plurality of FFs and the second FF of the second plurality of FFsoperate within a first clock domain; and the third FF of the secondplurality of FFs and the fourth FF of the second plurality of FFsoperate within a second clock domain.
 7. The apparatus of claim 1,wherein: only the first FF of the first plurality of FFs is interposedbetween the first thermometer encoder and the ADC; and only the secondFF of the first plurality of FFs is interposed between the secondthermometer encoder and the ADC.
 8. The apparatus of claim 1, wherein:the first de-multiplexing stage and the second de-multiplexing stagecooperatively support a 1 to N de-multiplex level; and N is an integer.9. The apparatus of claim 1, further comprising: a plurality ofdistributed clock generators implemented to generate the third clock andthe fourth clock; and wherein: each distributed clock generator of thedistributed clock generators is reset simultaneously.
 10. The apparatusof claim 1, wherein: the apparatus is implemented within a communicationdevice; and the communication device is implemented within at least oneof a satellite communication system, a wireless communication system, awired communication system, and a fiber-optic communication system. 11.An apparatus, comprising: a plurality of distributed clock generatorsimplemented to generate a plurality of clock signals including the firstclock, wherein: each distributed clock generator of the distributedclock generators is reset simultaneously; the plurality of clock signalsincludes a first clock, a second clock, a third clock, and a fourthclock; an analog to digital converter (ADC) that digitally samples asignal at the first clock; a first de-multiplexing stage that includes afirst plurality of flip-flops (FFs) and a plurality of thermometerencoders, wherein: a first FF of the first plurality of FFs, that isclocked at the second clock, receives the digitally sampled signal fromthe ADC; a second FF of the first plurality of FFs, that is clocked atan inverted version of the second clock, receives the digitally sampledsignal from the ADC; a first thermometer encoder of the plurality ofthermometer encoders transforms thermometer coded data output from thefirst FF of the first plurality of FFs to binary data; and a secondthermometer encoder of the plurality of thermometer encoders transformsthermometer coded data output from the second FF of the first pluralityof FFs to binary data; and a second de-multiplexing stage that includesa second plurality of FFs, wherein: a first FF of the second pluralityof FFs, that is clocked at a third clock, receives the binary dataoutput from the first thermometer encoder; a second FF of the secondplurality of FFs, that is clocked at an inverted version of the thirdclock, receives the binary data output from the first thermometerencoder; a third FF of the second plurality of FFs, that is clocked at afourth clock, receives the binary data output from the secondthermometer encoder; and a fourth FF of the second plurality of FFs,that is clocked at an inverted version of the fourth clock, receives thebinary data output from the second thermometer encoder; and wherein:de-multiplexed binary data are output from the second plurality of FFs;only the first FF of the first plurality of FFs is interposed betweenthe first thermometer encoder and the ADC; and only the second FF of thefirst plurality of FFs is interposed between the second thermometerencoder and the ADC.
 12. The apparatus of claim 11, wherein: a rate ofthe second clock is one-half of a rate of the first clock; and a rate ofthe third clock is one-half of a rate of the second clock.
 13. Theapparatus of claim 11, wherein: the second plurality of FFs includes: afifth FF, coupled to the first FF of the second plurality of FFs, thatoutputs binary data there from on a falling edge or rising edge of thethird clock; a sixth FF, coupled to the second FF of the secondplurality of FFs, that outputs binary data there from on a falling edgeor rising edge of the third clock; a seventh FF, coupled to the third FFof the second plurality of FFs, that outputs binary data there from on afalling edge or rising edge of the fourth clock; a eighth FF, coupled tothe fourth FF of the second plurality of FFs, that outputs binary datathere from on a falling edge or rising edge of the fourth clock; and thefifth FF, the sixth FF, the seventh FF, and the eighth FF output theircorresponding binary data simultaneously with one another.
 14. Theapparatus of claim 11, wherein: the first FF of the second plurality ofFFs and the second FF of the second plurality of FFs operate within afirst clock domain; and the third FF of the second plurality of FFs andthe fourth FF of the second plurality of FFs operate within a secondclock domain.
 15. The apparatus of claim 11, wherein: the firstde-multiplexing stage and the second de-multiplexing stage cooperativelysupport a 1 to N de-multiplex level; and N is an integer.
 16. Theapparatus of claim 11, wherein: the apparatus is implemented within acommunication device; and the communication device is implemented withinat least one of a satellite communication system, a wirelesscommunication system, a wired communication system, and a fiber-opticcommunication system.
 17. An apparatus, comprising: an analog to digitalconverter (ADC) that digitally samples a signal at a first clock; afirst de-multiplexing stage that includes a first plurality offlip-flops (FFs) and a plurality of thermometer encoders, wherein: afirst FF of the first plurality of FFs, that is clocked at a secondclock, receives the digitally sampled signal from the ADC; a second FFof the first plurality of FFs, that is clocked at an inverted version ofthe second clock, receives the digitally sampled signal from the ADC; afirst thermometer encoder of the plurality of thermometer encoderstransforms thermometer coded data output from the first FF of the firstplurality of FFs to binary data; and a second thermometer encoder of theplurality of thermometer encoders transforms thermometer coded dataoutput from the second FF of the first plurality of FFs to binary data;and a second de-multiplexing stage that includes a second plurality ofFFs, wherein: a first FF of the second plurality of FFs, that is clockedat a third clock that is generated using the second clock, receives thebinary data output from the first thermometer encoder; a second FF ofthe second plurality of FFs, that is clocked at an inverted version ofthe third clock, receives the binary data output from the firstthermometer encoder; a third FF of the second plurality of FFs, that isclocked at a fourth clock that is generated using the second clock,receives the binary data output from the second thermometer encoder; anda fourth FF of the second plurality of FFs, that is clocked at aninverted version of the fourth clock, receives the binary data outputfrom the second thermometer encoder; and wherein: de-multiplexed binarydata are output from the second plurality of FFs; the first FF of thesecond plurality of FFs and the second FF of the second plurality of FFsoperate within a first clock domain; the third FF of the secondplurality of FFs and the fourth FF of the second plurality of FFsoperate within a second clock domain; a rate of the second clock isone-half of a rate of the first clock; a rate of the third clock isone-half of a rate of the second clock; the first de-multiplexing stageand the second de-multiplexing stage cooperatively support a 1 to Nde-multiplex level; and N is an integer.
 18. The apparatus of claim 17,further comprising: a plurality of distributed clock generatorsimplemented to generate the third clock and the fourth clock; andwherein: each distributed clock generator of the distributed clockgenerators is reset simultaneously.
 19. The apparatus of claim 17,wherein: the second plurality of FFs includes: a fifth FF, coupled tothe first FF of the second plurality of FFs, that outputs binary datathere from on a falling edge or rising edge of the third clock; a sixthFF, coupled to the second FF of the second plurality of FFs, thatoutputs binary data there from on a falling edge or rising edge of thethird clock; a seventh FF, coupled to the third FF of the secondplurality of FFs, that outputs binary data there from on a falling edgeor rising edge of the fourth clock; a eighth FF, coupled to the fourthFF of the second plurality of FFs, that outputs binary data there fromon a falling edge or rising edge of the fourth clock; the fifth FF, thesixth FF, the seventh FF, and the eighth FF output their correspondingbinary data simultaneously with one another; only the first FF of thefirst plurality of FFs is interposed between the first thermometerencoder and the ADC; and only the second FF of the first plurality ofFFs is interposed between the second thermometer encoder and the ADC.20. The apparatus of claim 17, wherein: the apparatus is implementedwithin a communication device; and the communication device isimplemented within at least one of a satellite communication system, awireless communication system, a wired communication system, and afiber-optic communication system.